Figured I would share my design of the front panel of the Banggood () that I have seen a lot of people using.? Im not a graphic designer or a designer of any sort so please edit this as you like or see fit and contribute your edits as you want.? Currently the basic design of this is that the uBITX mainboard, raduino, and LCD all just drop in.

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OK, a few more words about what's going on inside the si5351.
Perhaps more than you really want to hear.

Assume you are tuned into a CW station at 7.1mhz.
We have a? single conversion superhet such as the Bitx40, the VFO is 7.1 mhz above
our 12mhz intermediate frequency, so 19.1mhz.? The Si5351 is providing that VFO.

But the Si5351 only has an 875mhz reference oscillator, it has to do some sophisticated math inside
to create that 19.1mhz VFO.? And that math sometimes has rounding errors.
Most of the time the VFO is right at 19.1mhz, but it does occasionally jump around a little bit,?
in extreme cases by a kilohertz or more.? So in addition to letting you hear that 7.1 mhz station,
your radio might also be letting through bits and pieces of other stations at 7.099 or 7.101 mhz, if only?
for a millionth of a second or so.? Those bits and pieces add up, they sound like noise.?
Specifically, phase noise.

To reduce that phase noise requires better computations inside the si5351, and that requires more power.
?


Here's a brief example of the sort of math that goes on inside the Si5351:
Assume we have a 875mhz reference, and want to generate a 19.1mhz signal.
We an get close by dividing by 46, giving 19.0217 mhz out.
We can divide by 45, to get 19.4444 mhz.
If we mostly divide by 46, and sometimes divide by 45, it can average out to exactly 19.1 mhz,
but if you look close you can still tell that it is just jumping between 19.0217 and 19.4444 mhz out.
Some serious phase noise.
This is called a fractional divider, because it is dividing by something between the integers 45 and 46.

That's what SiLabs does, except they also add a programmable delay line to the output pin.
They delay the rising and falling clock edges a few picoseconds, differently for each clock edge,
doing calculations with each clock edge to determine how much delay is needed to make the output
look like a 19.1mhz square wave.? Those calculations aren't perfect, nor is the delay line.?
So we still get some residual phase noise.

The Si5351 operates in two stages, first stage brings the 25mhz crystal oscillator up to around 875mhz.
This involves a second fractional divider much like the one described above.
In this case, 875/25 = 35.0 exactly, but that figure of 875 could have been anything between 600 and 900 mhz.

Jerry._,_._,_