On Wed, 18 Dec 2019, Ashhar Farhan wrote:
Jack and others,
I have uploaded the refactored code to?.
I will document this further in the next few days.?
When you did the refactoring, did you incorporate the suggestion someone made last week to create IFDEF conditionals so that the new code can support older versions of the hardware?
I have a v5 board with the standard 2-line display. Transmit seems to work fine, as I was able to check it with a friend's spectrum analyzer, but receive does not work at all. My friend suggested that it is so far out of calibration that the signals are outside the filter passband. Since I can't 'tune in to a strong signal', I'm stalled at the first step in the calibration/alignment procedure. I'm wondering if the 'new improved' calibration procedure in the V6 firmware might include a workaround for this stumbling block?
I don't have access to a good signal generator, but I do have a working frequency counter. Is there a test point that you can point out to me where I can sample the master (or derived) clock signals. I could play with the calibration values until the clock freq corresponds to the display freq.
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Rick Green N8BJX
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