Give it a try and report back. It's an interesting idea.
1. What are the required AVC attack and decay times vs, the Nano maximum ADC read rate plus the added I2C/SPI pot communications overhead?
2. Can loop() tolerate any more overhead without impacting the operability of the UI? Adding another processor defeats the original premise of a minimal part count implementation. Maybe it could be implemented in an ISR, but I believe that I read awhile back of issues with I2C and ISRs. Find/develop a custom I2C library?
