Hi,
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I just received a Arduino MKR Vidor board. It is a higher powered Arduino with a medium sized FPGA included on the board.?
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My thought was to add a fairly fast (around 120Mhz to allow oversampling) 10 or 12 bit DAC to supply the transmit signal directly to the low pass filter at Test Point 1. And use a 50Mhz 12 bit ADC (again to allow oversampling) for receive picking up the signal at test point 17.?
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For receive this should be better than trying to push the ADC close to the antenna, as the digital receiver will then have a fairly cleaned up signal to work with and the signal frequency (12Mhz) is fairly moderate. In fact, if the frequency could be mixed down even lower, it might be possible to use fairly low speed ADCs.
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Another advantage of the band pass filtering ahead of the ADC for receive is there should be no need for quadrature (I/Q) mixers, and dual ADCs, as the digital processing will not need to determine which signal frequencies are above and below the center frequency. (Internally, for SSB demodulation, depending on method, there could be I/Q processing. But that can all be handled in the FPGA).?
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So the uBITX could be a really good starting point for the RF parts of a FPGA SDR transceiver. It's possible the specs for the ADC and DAC chips could be toned down a bit and reduce the costs further.?
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Here are a couple of possible designs that could be used as a starting point.
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Tom, wb6b
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