I agree with the other posts on this thread that level shifters are not needed. Pulling up the lines to 3.3v will work fine with 5v level signals since it crosses the upper (On) threshold.
I do want to clear up a few things.
1: The data signal is bidirectional but the clock is always provided by the master. In single master mode (most commonly used) this signal is technically unidirectional. (That's one nit picked!)
2: The exact value used for the terminating (pull-up) resistors is not critical but remember that the lower resistance value from multiple resistors on the line means that the devices have to sink more current. This could cause issues with either the pin on the device eventually burning out or the signal not being pull low enough. The total resistance should be somewhere in the area of about 10K +/- 50%. I recommend to try to get as close to 10K as you reasonable can. If you want something different then read the spec sheets to see how much current these pins can sink. Too much resistance will cause the edge of the signal to round or ramp up instead of sharply rising. Too little resistance can cause the signal edge to ring. If this become severe it can cause issues. There are filters on the devices to deal with these issues but they can only do so much. The signal edges of the clock are most important. The data signal needs to be stable at the time it is sampled starting on the rising edge of the clock and continued stable until the falling edge of the clock. See spec sheets for more info.
3: If all the devices are in close proximity the placement of the resistors are not critical. However as the lines get longer or many devices are placed on the I2C bus the resistor placement can become critical. On a single master system the master should be at one end of the bus and the terminating resistors at the other end. In a multi master system there should be terminating resistors on each end of the bus. Resistors in the middle of the bus can potentially cause weirdness on the signal edges due to reflection.?If you are using a lot of devices or long lines then you should scope the lines to see the signal edges to determine how much resistance should be used.??Do also pay attention to the voltage supply line to the resistors. Some resistance or noise in this line can cause issues.
4: It is possible to have multiple masters on the bus but it is more complicated. The driver software needs to support this mode. Most drivers do not support it.
5: Many of the arduino drivers do support both master and slave modes. I have used the slave mode when I needed a second processor to deal with a cpu intensive sensor so that the master could handle everything else.
6:?TWI (Two-Wire Interface) is just another name for I2C. Sometimes other similar names with references to "Two Wire" are used. To add to the confusion there are similar standards that may or may not be compatible. For example, the CAN bus often used in cars is similar and sometimes devices for one bus may (or may not) work on the other. YMMV
My comments may make I2C sound hard but it really isn't. I usually just slap a few I2C devices on a controller and go with it. Only if you start pushing things do you need to worry about all the details. Main thing is to just make sure the resistors are connected to the correct voltage and there should only be one (or maybe two) per line. Do note that many of the little I2C modules you find often have the resistors (SMD) attached. You may need to remove them as needed. A few boards have jumpers (closely spaced solder pads) that allow you to enable/disable these resistors.
One more thing that I see people getting flustered with I2C. I2C addresses can be confusing. There are several different ways to specify an I2C address. First, most people use hex numbers but sometimes someone will use decimal. A more confounding problem is due to the way the address is passed on the bus. Technically the address is 8 bits with all the odd addresses are read and even addresses are writes. (Confused already?) Chip manufacturers like to list the address write/read pairs. Software, however, likes to specify just the top 7 bits and then shift 1 bit left.? The 0 bit is then treated as a write/read flag. See example below:
Given the following 8 address bits
10100010
Hex = A2 write address, 10100011 (A3) is the matching read address
Decimal = 162 write address, 163 read address
Adjusted = 1010001 = Hex 51, Decimal 81 for both read and write.
See how the adjusted binary is just the upper 7 bits so the 8 bit format is 1010001X where X is 0 for read and 1 for write.
Oops, I think I may have just hijacked this thread. Once I get started it's hard to stop.
Dale
KJ4C
