Yup, delays on those i2c writes could be revealing. ?Occurred to me but I haven't gotten around to it. ? ?But I did put a scope on it, looked at the 7mhz waveform with 5ms of delayed sweep after triggering on an edge. ?Seemed clean. ?The important thing for me is it sounds clean on the SW receiver, even when going through a transition between one integer and the next.
On p20 of the Si5338 datasheet ? ?
they quickly mention how they clean up those edges. ?I'd guess the mechanism is the same as the phase adjustment they make available to us, which is not infinitely accurate.?
> ? ?To eliminate phase error generated by this process, the MultiSynth block calculates
> ? ?the relative phase difference between the clock produced by the fractional-N divider
> ? ?and the desired output clock and dynamically adjusts the phase to match the ideal clock waveform.
In the next paragraph they mention how it's good for any frequency up to vco/8.0, and then integer divides of 6 and 4. ?Just like the Si5351. ?At $10, the Si5338 was apparently able to afford a tech writer. ?So the Si5338 docs might be a good way to fill in holes left by the Si5351 docs.
Jerry, KE7ER
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On Fr, Jun 30, 2017 at 01:52 am, Hans Summers wrote:
It would be very interesting to slow everything down so that the I2C update of the 8 registers takes 5ms. In other words - remove the delay(5), and perhaps have an output pin toggling so that you can hook on an oscillscope and see how often the output frequency is being updated. Then put delays in the I2C write - so that each step takes 5ms. It would be very interesting to see what happens then!
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