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When I wrote my previous message that mentioned latency, I could have been more clear. I blame jet lag and diving back into the T41 project right after a vacation. This discussion might be confusing

I'd like to throw in a couple of things to this great discussion from a systems perspective. In respect of latency one could ask questions like these perhaps: Does/will it exist? Does it matter, and

Having written a lot of code for Hermes and Apache Labs radios I can assure that it does not do all the DSP work in the FPGA. On the receive side the hardware ADC samples 64 MHz of spectrum with 24

I was gonna say… from what I’ve seen… even the Hermes project… the FPGA did all of the digital processing including FP DSP… but the A/D, D/A, and analog filters were all external to the

Wes et al.: The processor of the Teensy 4.0 and 4.1 does have parallel functionality.? It has a 6-stage *superscalar* pipeline. This project was born from source code that provided us many

Yes, so do many many others like the RadioBerry, the HPSDR hardware, the QSR1, Prometheus, etc… all open source. Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ

Don’t know which of us you are responding to but the difference between Teensy 4.1 and an FPGA processing is not latency. It is abrupt interruption of processing and odd consequences of what happens

Here in the USA our ARRL is fighting the proposed use of HF for "high frequency trading".? Wall Street stock traders on HF! I suppose wireless is the minimal latency that is physically possible.?

Hmm, latency in radio comms. Just for grins, I chose my home QTH and the first place I could think of in Australia, which was Adelaide, Turns out that the distance is about 9,184 miles as the 747

Flex uses fpga for all the processing [email protected]> wrote:

I think you will have problems implementing the DSP functions in the FPGA.? It is fairly easy to get samples from an A-D or D-A and do some processing on it to implement a DDC or DUC, but to do any

What you say works for regular processors, even with multiple cores. Not for FPGAs. They always have many thread-equivalent tasks running independent of the rest. They CAN communicate if you want them

Wes: You're right that all SDR's suffer some degree of latency. The real question is: "How much?" Using the Teensy 4.1 is nowhere near the performance of an SDR based on the Intel I9 processor.

Late to the discussion, but.. those are dangerous words. :-) The primary rule of real-time programming is that software must never cause a task to miss its timing deadline. The corollary is that when

Hi Bruce… Thanks for the note. I’m just back from three weeks in the Caribbean at my contest station and teaching classes for the fall semester now (at least for the next few weeks). I’m back to

K9HZ: I am very new to this so I may just not where to look. I am waiting for new boards for v1.2 (latest now in beta). I bought your 20W rf amplifier and am currently assembling it. I bought thru

Its moving along. I just returned home from 3 weeks at my contest station in the Caribbean where my wife had me replacing the wood floors in our villas… so glad to be home working on my own projects

Bill, good afternoon.? I haven't heard from the stream lately regarding progress on this board development.? Is the development complete or at a convenient pause?? ?If the latter, what's left to

Depends how basic you want to start.? I use National Instruments Multisim and Elvis platform to do prototyping and enhance my learnings as I'm not an EE.? There is a reasonable starter FPGA starter

Bemicro used to have a nice development board with an Altera FPGA that was a reasonable price. I have one that is part of an iquadlabs SDR transceiver. Unfortunately I don't think they are available