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-------- Original message --------From: "John Melton via groups.io" <john.d.melton@...> Date: 2023-10-07 10:01 a.m. (GMT-05:00) To: [email protected] Subject:

FWIW Flex actually split the processing between their fpga and TI DSP chips (TMS320). See this video for some more info: https://www.youtube.com/watch?v=eE_c-dSEu4E

See below: Jack, W8TEE

Bill: I am responding this way as I can't read your email address. The ending is blocked and I don't know how to get around that. I became a ham in Dec 2021. Passed Basic with Honours. So I am very

Bruce, you can send eMails to bill@... <mailto:bill@...> I get them 24/7 Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ Owner - Operator Big

I ordered another 200 boards for the K9HZ 20W PA last week. they will be here next week. I have about 5 kits left but hope to have at least 100 kits ready just after CQWW. Dr. William J. Schmidt -

Picture please! I’ll get you situated! Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ Owner - Operator Big Signal Ranch – K9ZC Staunton, Illinois Owner –

Don't know how to send this to one person as K9HZ probably has to answer this. In winding L2 I find I cannot get 7 turns done I am a little short - maybe not strong enough to pull it tighter. My

The superscalar aspect of the pipelines was when they added additional execution units to handle branch prediction so that they could compute both paths. As they added more simultaneous instructions

Somewhere I have an article about the DSP/CPU versus FPGA wars of the late 1990s/early 2000s. FPGA won!? Even though FPGAs clock at much slower speeds, the ability to transform data in a single clock

*** My understanding of "hyperthreading" is that it's just multiple sets of CPU registers. I did a project with an 8051 back in the 80's. The '51 had two sets of registers aka "register banks" that

Also, here is the originator of that Trenz “teensy” style fpga board that is manufactured by Trenz in Germany (I think): https://blackmesalabs.wordpress.com/

Here is what looks to be a really good fft implementation (for fpga). https://github.com/ZipCPU/dblclockfft The author - Dan Guisselquist, seems to be fairly knowledgeable about FPGA development. If

https://opencores.org is a good place to start -- John G0ORX

I would like to start a list with free sources for IP. Thats where my interests lies at the moment. Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ Owner - Operator Big

Yeah, I just jumped in to try to help folks understand that the RT1062 has plenty of “horse power.”? Then it seemed that some did not understand pipelining or superscalar when I quoted from the

It’s kind of interesting where this discussion has gone. Ian’s clothing description is describing what’s called ‘pipelining’ its where you break a higher level function into smaller parts,

Jerry: A quick look at Wikipedia reveals:? "A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor." In pipelining,

*** Does this mean that it can execute six instructions at the same time ( assuming no data dependencies )? - Jerry, KF6VB