¿ªÔÆÌåÓý

ctrl + shift + ? for shortcuts
© 2025 Groups.io

Examples of anomalous ADC system that a NanoVNA is NOT good for


 

Attached are a couple plots of the processed digital output of an ADC, where there was leakage of an external clock signal into the system.? Sample rate is about 49.2 MHz, interference signal is 66 MHz, Signal being digitized is ~110 MHz (aliased down to about 12 MHz) - 12 bit ADC

You can see that there's really no direct sign of the 66 MHz in the output (e.g. 66 MHz would have aliased to 1.34 MHz), but there's plenty of IMD with the interaction of the 66MHz and the 110 MHz/12 MHz input


 

On 2/26/22 8:54 AM, Jim Lux wrote:
Attached are a couple plots of the processed digital output of an ADC, where there was leakage of an external clock signal into the system.? Sample rate is about 49.2 MHz, interference signal is 66 MHz, Signal being digitized is ~110 MHz (aliased down to about 12 MHz) - 12 bit ADC

You can see that there's really no direct sign of the 66 MHz in the output (e.g. 66 MHz would have aliased to 1.34 MHz), but there's plenty of IMD with the interaction of the 66MHz and the 110 MHz/12 MHz input
Excuse me - 66 MHz aliases to 16.8 MHz ( 66/49.2 = 1.34 - 1 = 0.34 * 49.2 = 16.8)? - Too early in the morning.






 

Jim, I was working for HP when Tektronix loaned us one of their early
engineering models of their FFT'ed spectrum analyzer. They just requested
we document what we found. Well,..... it was OK on discrete single-signal
inputs, but,....... with digitally modulated signals, it severely aliased
throughout its RF range. We assured there was no overload and that we were
operating it well below anything that might have influenced its behavior.
A month later, we gave it back to Tek with only one comment - that which I
have related. As far as application with digital circuitry and equipment,
it was useless.

Dave - W?LEV

On Sat, Feb 26, 2022 at 4:55 PM Jim Lux <jim@...> wrote:

Attached are a couple plots of the processed digital output of an ADC,
where there was leakage of an external clock signal into the system.
Sample rate is about 49.2 MHz, interference signal is 66 MHz, Signal
being digitized is ~110 MHz (aliased down to about 12 MHz) - 12 bit ADC

You can see that there's really no direct sign of the 66 MHz in the
output (e.g. 66 MHz would have aliased to 1.34 MHz), but there's plenty
of IMD with the interaction of the 66MHz and the 110 MHz/12 MHz input





--
*Dave - W?LEV*
*Just Let Darwin Work*