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While described as 101 fixed steps,
fewer are evidently used by nanoVNA firmware for small spans.
Given Si5351 setting granularity for artifact-free switching,
what are rule-of-thumb minimum frequency increments
over the full range?

I see on the schematic that the vctcxo has its frequency driven by the DAC
output, is this used as a way to have finer frequency steps ?

Thanks, yes I was looking at the original schematic on GitHub by edy555 as
I was not aware of the differences.

I hope the V2 will have it back, or be layed out in such a way we can
solder one.
With the adf4350 and depending on the chosen phase detector frequency (PDF
or PFD) the resulting large frequency steps may be inconvenient in some
cases as the minimal step is PDF/divisor where divisor is constrained over
12 bits (4096 at most). 26MHz/4096 gives something in the order of 6Khz,
this would be the minimal step for the range 4400-2200 Mhz, other ranges
are obtained by a division which also divides the minimal step.
The PDF can be set lower, but at the expense of the phase noise. The phase
noise itself reappears in full on the 5Khz signal which is used for the
phase measurement, so some care has to be taken when designing the
compromise.

Please object or complement this analysis. I don't know the SI5351 so I
can't tell much on the current design.

To get back to the initial question: zooming on a narrow frequency range
may be a true concern and it would be nice for the firmware to emit some
sort of warning if frequency points are too close for the hardware to
synthetise them.

The hardware differences between the commercial and the initial edy555
hardware also raises the question whether the DAC to frequency control of
the vctcxo is used by the edy555 firmware for small frequencybsteps
adjustments.
I have not looked (yet).

Regards
Jose


On Wed, Oct 9, 2019, 00:52 Jose Luu via Groups.Io <jose.luu=
[email protected]> wrote:

Thanks, yes I was looking at the original schematic on GitHub by edy555 as
I was not aware of the differences.

I hope the V2 will have it back, or be layed out in such a way we can
solder one.
With the adf4350 and depending on the chosen phase detector frequency (PDF
or PFD) the resulting large frequency steps may be inconvenient in some
cases as the minimal step is PDF/divisor where divisor is constrained over
12 bits (4096 at most). 26MHz/4096 gives something in the order of 6Khz,
this would be the minimal step for the range 4400-2200 Mhz, other ranges
are obtained by a division which also divides the minimal step.
The PDF can be set lower, but at the expense of the phase noise. The phase
noise itself reappears in full on the 5Khz signal which is used for the
phase measurement, so some care has to be taken when designing the
compromise.

Please object or complement this analysis. I don't know the SI5351 so I
can't tell much on the current design.

To get back to the initial question: zooming on a narrow frequency range
may be a true concern and it would be nice for the firmware to emit some
sort of warning if frequency points are too close for the hardware to
synthetise them.



On Tue, Oct 8, 2019, 20:47 Larry Rothman <nlroth@...> wrote:

You're looking at an old schematic. The latest schematic is at the end of
the July user guide in the files section. The tcxo no longer used that
line.



On Tue, 8 Oct 2019 at 8:21 PM, Jose Luu<jose.luu@...> wrote: I
see on the schematic that the vctcxo has its frequency driven by the DAC
output, is this used as a way to have finer frequency steps ?

On Tue, Oct 8, 2019, 09:27 Oristo <ormpoa@...> wrote:

While described as 101 fixed steps,
fewer are evidently used by nanoVNA firmware for small spans.
Given Si5351 setting granularity for artifact-free switching,
what are rule-of-thumb minimum frequency increments
over the full range?

On Tue, Oct 8, 2019 at 11:48 PM, Jose Luu wrote:

the question whether the DAC to frequency control of
the vctcxo is used by the edy555 firmware for small frequencybsteps
adjustments.

Frequency stepping in the current firmware is done only with the SI5351
Early firmwares explicitly rounded the requested frequency to multiples of 100 making it impossible to do small steps
The current edy555 firmware does no longer do the rounding.

zooming on a narrow frequency range may be a true concern

It is e.g. for me

and it would be nice for the firmware to emit some sort of warning
if frequency points are too close for the hardware to synthetise them.

Documented limits would IMO be even nicer, helping prospects consider
whether nanoVNA minimum frequency steps are appropriate for them.

si5351 allows to use frequency steps smaller than 1 Hz, but NanoVNA has limitation, it store frequency as integer value, so it cannot work with frequency step smaller than 1 Hz.

Also some old NanoVNA firmware has limitation to about 1-10 kHz span. But with latest firmware you can use 100 Hz span.

si5351 allows to use frequency steps smaller than 1 Hz, but NanoVNA has
limitation, it store frequency as integer value, so it cannot work with
frequency step smaller than 1 Hz.

I remember reading that some steps provoke artifacts, so were avoided.
Is this no longer true? 1 Hz steps at any frequency are now supported?

si5351 allows to use frequency steps smaller than 1 Hz,
but NanoVNA has limitation, it store frequency as integer value,
so it cannot work with frequency step smaller than 1 Hz

101 steps for 50kHz to 1500MHz spreads them thinly.
I appreciate the storage impact, and when not testing a particular DUT
tend to calibrate for 4 bands of roughly equal octaves:
50-658, 666-8660, 9800-114000, 126000-1500000
.. but it would seem more useful for nanoVNA to implement logarithmic rather than linear steps.

current firmware allows to use 1 Hz span. Tested with 100 Hz span, works ok.

TDR, phase delay, and other measurement needs linear frequency steps.