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TX Level control
I am trying to use any of the ways to change TX level to reduce drive to my PA on PSK modes
so that linearity is good. I am aware that the range of adjustment is limited, but I only need 3dB
or so of reduction.
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If I use the spot button and associated slider I can vary the output power between 0.0 and 6.1W
on 80m as shown by the power meter at the bottom of the window. Perfect!
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If I use the Config->HL2->Bands window to set a TX level of 10 on 80m (rather than the 255 max) and
use PTT to TX on FM I still get 6.1W, the level is not reduced.
?
If I use Config->Config and adjust the TX level down from 100% I still see no reduction, the output is
still 6.1W
?
This is on Windows 10 but I also see the same effect on Linux Mint. I tried the latest Quisk release and
also 4.2.37
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I am sure I have seen this work properly before so I must be doing something wrong.
Any ideas please?
?
73,? Neil? G4BRK |
Hi Christoph,
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Yes, but I would still expect to see a change in output, which I do not.
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I just reprogrammed the gateware to include TX on another HL2 and tried the same experiment.
On this one I see the expected change in power output with the Config->Config TX Level slider
and the band settings.
?
So it looks like there is a problem with the original HL2 hardware. That may be difficult to fix :-)
I tried a gateware reload but still get the same result.
I may have to repurpose this one for RX only service.
?
Thanks/73,
Neil? G4BRK |
Hi Jim, Thanks for the reply. I am using 73p2 file hl2b5up_main.rbf - this is identified as 4 RXs by SparkSDR If I load hl2b5up_cicrx.rbf? with 10 RX and no TX then the TX does not operate, as expected. I tried loading the factory gateware (shorting PTT and KEY to GND on the front panel) - this also identifies as 73p2 with 4 RX and still shows the problem. A different HL2, also with 73p2 main, works correctly and the TX power varies by approx 7.5 dB with the Config->Config TX Level slider. So it looks like a hardware problem on the first example, possibly a faulty AD9866 chip as the TX level is set within the chip, presumably via a register which is written by Quisk.? This seems a bit unlikely as I haven't seen any other issues with the operation of the HL2,? but I don't have any better suggestion. 73, Neil? G4BRK On Wed, 12 Mar 2025 at 17:32, jimahlstrom via <jahlstr=[email protected]> wrote:
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