On Wed, 2022-07-13 at 10:52 +0200, Axel Rau wrote:
For my project with THT footprints, I have 3 net classes.
What are best practices rules for dependency of
clearance, track width, via size ?
I'm not sure there are "best practices". It depends on your application and needs. As a vague general rule, leave as much copper on the board as possible, subject to routing constraints. On the other hand, thick wide tracks are more difficult to solder to if you have a weedy soldering iron and also have higher capacitance to a ground plane, if used. Narrow tracks are easier to route, but have higher resistance and inductance. If you have a large 2-sided PCB, you might want to avoid warp by balancing the amount of copper on each side. Most people never consider this. May be warp is of no consequence to you.
Clearances come down to: PCB fabricator rules for narrow gaps or required clearance and creepage distances for high voltage design.
Via sizes have little to with KiCad and much more to do with the acceptable rules of your PBC fabricator. They will specify the minimum drill size, the minimum annular ring, and the aspect ratio (hole size/board thickness). Provided you meet those limits, you can use more or less what you like.
There are other trade-offs, particularly if you are doing dense layout and/or RF layout, when via inductance might need to be considered. Vias also have a current limit, and a finite thermal resistance, which might need to be considered if you are doing power work.
Aesthetics is also another (personal) consideration.
Tony Casey