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PI controller time domain responce in PLL from AC responce

 
Edited

Hello,I have built a PI controller I have its time domain step responce and AC responce.
PI controller is supposed to help with the DC part of the error signal of a PLL system.
Thanks.
 

I doubt if your VCO has any DC response since it appears to be a high Q device.? Start with a model.? The more detailed the better you should try to show 2nd order effects or higher.? The VCO only needs direction information since amplitude out should not change.? If it does you will need to compensate for it to give you a descent lock in range.? Please note that the LT1128 only has a 50 MHz bandwidth which is probably not high enough for what you are trying to do.
 

I know that PI controller has an effect on the DC part of the error signal of the PLL,
Is there a way i could see this in a simulation?
Is there some example i can see the DC effect of the PI controller in the PLL?
Thanks.
 

You have access to the PLL in your lab.? Put a DC into it and observe the results.
?
 

Hello, some videos were made from my lab to demostrated the situation.
The main issue is the controller .
There is a PI controller I have simulated.
When I simulation amplifier then I can see the gain on my scope in my lab.
But here its not a regulat gain , its understanding based on the ltspice simulation how it will affect the drift DC in a pll system.
There is nothing could be done in LTspice to see based on AC responve how it will affect the drift in my DC error signal?
Thanks.
 

On Sun, Dec 15, 2024 at 01:45 PM, john23 wrote:
Hello, some videos were made from my lab to demostrated the situation.
The main issue is the controller .
There is a PI controller I have simulated.
When I simulation amplifier then I can see the gain on my scope in my lab.
But here its not a regulat gain , its understanding based on the ltspice simulation how it will affect the drift DC in a pll system.
There is nothing could be done in LTspice to see based on AC responve how it will affect the drift in my DC error signal?
I am only guessing here, because I do not understand the overall system.
?
I'm guessing that the "drift" you are worried about, happens because of the transfer function of the YIG VCO.? In other words, the DC voltage needed to get the right VCO frequency, drifts over time and temperature.? Yes?
?
And I'm guessing the amplifier using the LT1028 must be your error amplifier ("Servo amplifier").? It is approximately an integrator.? Therefore, it will attempt to drive its output voltage to whatever is needed to slew the VCO to the desired frequency.
?
But it can drive only to +/- 7 volts, or so.? Is that sufficient to always drive the VCO to the correct frequency, even accounting for the drift?
?
The .AC sweep in LTspice (if you extend the sweep down to 1 uHz or so) shows that the DC gain is nearly 150 dB.? It is not infinite, but it is quite large.? You could use a .DC sweep to actually simulate it at "DC".
?
You can simulate the drift in LTspice, by adding a variable voltage source at the VCO's input, to inject a variable DC voltage there.
?
Andy
?
 

Hello Andy ,This driver is being built to be connected to a PI Controller which needs to tune my YIG into the resonance of the resonator.
The data about the YIG and the resonance dip properties shown in the phots below.
given the Q factor of the resonance shown below and the properties of the FM coil which we are driving to tune the yig.
What circuit properties you think I need to to have for my controller ?
Thanks.
sesitivity: 450 KHz/mA
3dB bandwidth 2.2MHz
resistance 2Ohm
inductance 1.5uH
/g/electronics101/photo/296358/3868513?p=Created%2C%2C%2C20%2C2%2C0%2C0
/g/electronics101/photo/296358/3868514?p=Created%2C%2C%2C20%2C2%2C0%2C0
 

Hello The controller needs to sweep over the area where the resonance is.
Its frequency range is 2MHz , what controller specs can I take from this requirement?

Also I was told that I need to plot error signal Vs frequency responce for designing the controller.
But my YIG has a drift so its not so stable.
Also error signal needs to go to some controller driver in order to have the frequency responce of the FLL.
What is the strategy for designing the controller of the FLL?
Thanks.
 
Edited

UPDATE:
My system is a frequency locked loop, by the diagram bellow, I intend to make a plot of a frequency Vs error signal as shown below.
Given this plot how would it help me to know the controller parameters i should use when building the controller?
Thanks.
/g/electronics101/photo/296358/3868979?p=Created%2C%2C%2C20%2C2%2C0%2C0
/g/electronics101/photo/296358/3868978?p=Created%2C%2C%2C20%2C2%2C0%2C0
 

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Good grief, John.

Unless your system is really (I mean REALLY) poorly behaved (seriously non-linear frequency vs. control voltage with discontinuities and reversals), a simple proportional control, perhaps with a little damping will work perfectly. I can't understand why you insist on making this whole thing so complicated. P+I is overkill for almost all control situations that I've encountered. If you really need to drive the long-term frequency error to zero, you may need a little Integral control, but that is a very rare need. (Again, just my experience.)

Do you have any hardware to just try some experiments? Is the hardware so expensive that you are spending weeks and months (of your own and others' time) trying to get a fictional simulation that may (or likely won't, as near as I can tell from all the chatter) give you a clue about what values to use? Grab your pll; set up its VCO to operate near your center frequency; make sure your reference frequency is stable; take the error output and divide it down with a couple of resistors (or amplify it, if it's too small - rarely needed!); feed that back into the control input and see if the output frequency matches what you want. There's no reason for it to be so difficult.

By the way, I don't think in any of these email threads you've actually told us what your objective is. What is the REAL problem you are trying to solve? You keep asking "how do I fasten these two boards?" when your real question is "how do I build a house?"

Donald.

On 12/20/24 06:19, john23 via groups.io wrote:

[Edited Message Follows]

UPDATE:
My system is a frequency locked loop, by the diagram bellow, I intend to make a plot of a frequency Vs error signal as shown below.
Given this plot how would it help me to know the controller parameters i should use when building the controller?
Thanks.
/g/electronics101/photo/296358/3868979?p=Created%2C%2C%2C20%2C2%2C0%2C0
/g/electronics101/photo/296358/3868978?p=Created%2C%2C%2C20%2C2%2C0%2C0
 

On Fri, Dec 20, 2024 at 06:18 AM, john23 wrote:
My system is a frequency locked loop, ...
I could swear you said it was a phase locked loop.
?
I get the feeling you do not seem to know what you are doing.? Am I mistaken?
?
Andy
?
 
Edited

Hello , I plugged a signal generator into point A of my system(as shown in the diagram and reccorded the error signal voltage which comes out from the mixer(POINT B).The plot below is based on crude manual point writing .At 9518Mhz we have error 0mV , there is a frequency range shown in red arrow where we have crude linear dependancy between frequency and error.
After the red frequency range the error behaves the opposite, exactly in the diagram photo below.
Matlab code is attached.

What steps do I need to do next to know what is the? condtroller behavior should I use for locking?
Video of the setup and measurment is attached in the link.

/g/electronics101/photo/296358/3868979?p=Created%2C%2C%2C20%2C2%2C0%2C0
/g/electronics101/photo/296358/3868978?p=Created%2C%2C%2C20%2C2%2C0%2C0
/g/electronics101/photo/296358/3869434?p=Created%2C%2C%2C20%2C2%2C0%2C0
/g/electronics101/photo/296358/3869468?p=Created%2C%2C%2C20%2C2%2C0%2C0



 
freq_up=[9516.89,9517.6,9517.69,9517.81,9517.83,9517.86,9517.9,9518,9518.05,9518.07,9518.1,9518.13,9518.18,9518.33,9518.45,9518.68,9519.01,9520.3]
error_up=[40,47,52,31,26,13,3,-0.4,-3.7,-8.3,-13.5,-25,-39,-35,-30,-24,-18,-1]
plot(freq_up,error_up)
xlabel('frequency [MHz]')
ylabel('error signal mixer phase detevtor[mV]')
?

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