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Dear All I'm going to do my first PSU... tnx for this amazing tool that is PSUD. I am implementing a PSU for an high quality line stage. The load on the PSU will not be more than 40ma and the final B+ should be about 250V. I have several EZ81 around, so that will me my rectifier. The PSU will be a CLCLC. I hope somebody can help with this: 1. I read that it's better to put a resistor in series with the EZ81 between the secondary and the tube, what do you think? Any experience with that? 2. I was told that it's best to have the first cap really small, something below 15uF. I saw cases where people use a first cap of 47uF and cases where people use 1uF... what's the sonic difference? I tried to simulate both, of course I get different ripple and mostly different rise time. I'm interested in sound, do these choice impact sound significantly? I hope somebody is willing to help Best Wishes to all Pierre

Can the max vac on the sec of the plate xfmr be increased...... like up to 15 kvac ? As is, it's maxed at 10 kvac. ( aprx 14.14 kvdc with a FWB and C input filter). I was trying to simulate a 21 kvdc B+ supply...and can't. That was for a water cooled transmit tube. In other cases, 30 kvdc is required for a hi-pot tester....( for testing insulation break down, or between elements in a tube). Used for all sorts of various applications. is this difficult to add on ? Or can it be part of the ....'PSUD-3' ?

Hello, I use a common mode choke in my power supplies, but I'm really just guessing about the results I'm getting. I'd prefer to model them in software, but I can't figure out how to include one in yours. See Fig. 8: https://www.circuitfeed.com/home/analog-circuit/power-supply/rectifiers/uncontrolled-rectifier/bridge-rectifiers-calculation-filter-circuit-diagram-and-working/ Except in my circuits, the +/- rails are split with the ground in the center. I use a rail splitter circuit for that. His simulation seems to show very good performance, but I'd like to be able to do this in your software. I've tried to do it in a spice simulator like Tina Ti, but I can't get it to work. That's why I prefer your software. Thanks.

Hello Looking for ways to make PSUD work on my Apple computer (M1 chip). I am running macOS or Linux (in a virtual ARM machine). Thanks for any hints or ideas!

Hello, Trying to dersign a circuit for a super regulated and smoothes 5v linear power supply for a DAC. Does anyone know where the PSUD2 download is located? Thanks Joe

I’m looking to download the software for MAC but somehow I can’t find any software download on /g/duncanampspsud Thanks

On a simple FWB rectifier with a high C filter cap....... is the result RMS I(C1)..... the same as the AC ripple current going into the cap ??? On another note ( using the same above config) I noticed that the RMS xfmr current I (T1) x RMS V(T1) results in a LOT more rms AC power..... vs just the V(L1) x I (L1)..... like a lot more, like 53.7% more. Put another way DC load power / AC power = .65 Am I assuming the Power factor is just .65? On another note ( using the same above FWB + filter cap config).....when comparing V (T1) vs I (T1) ...under full load..... that the peak of the current pulse sits dead center in the middle of the (now flattened to a straight line) peak of the voltage. I believe the flattened Voltage portion is what is causing the harmonics going back into the mains V. It also appears that there is no leading / lagging going on. The top of the current pulse is dead center in the flattened portion of the top of the voltage peak. Since there appears to be no leading / lagging..... where is the lousy...'apparent power factor' coming from ?? The config is as follows. Plate xfmr with 240 vac input ( 60 hz)....and a 5225 vac secondary ( no load). Hypersil C core xfmr. .1 ohm dc pri resistance. And a 6.0 ohm dc sec resistance. Source resistance = 53.39 ohms. Sec winding rated at 3 amps CCS. Xfmr weight = 253 lbs. FWB consists of 24 x 6A10 diodes ) 1 kv piv / 6 amps CCS / 400 amps surge rated) in series for EACH of the 4 x legs of the FWB. Then two identical FWB assy's are wired in parallel. 192 x diodes in total used. Filter cap is 800 uf ( 25 x 10,000uf @ 450 vdc lytics in series, each with a 100k @ 3 watt, 1% MOF across each cap ( aka...'eq' resistors). 2 x banks of caps are wired in parallel ( 400+400 = 800 uf). Each cap is just .0159 ohm for ESR @ 120 hz. Total for the 50 x lytics = .19875 ohms. Each lytic is 3.0" diam x 8.625" tall.. .and weigh 3.3 lbs each. Ripple current rated at 21.6 amps CCS. I have been using PSUD-2 in various high voltage configurations for eons now. FWCT, FWB, FWD. Plane C filter....and also a C-L-C configuration . For the C1-L-C2 config, I noticed that the C2 cap has to be a bare minimum of at least the same value as the C1 cap....and preferably a lot more. If the C2 cap is lower than the C1 cap value, the output DC voltage oscillates wildly, till it finally settles down. I also have the option of shunting out the L ( via a vacuum relay) to turn it into one big C filter. I also installed an adjustable spark gap across the 4H choke terminals. ( choke is also a hypersil C core type, 127 lbs, and rated for 3 amps CCS and 10 kvdc). For safety purposes, the entire choke is well insulated from the bottom of the rack cabinet. I have built plenty of HV B+ supplies over the years. I'm just not clear on the 'apparent PF' issue, V flattening / harmonics . AC ripple measurements. Any insight would be greatly appreciated.

Hi, I've been trying to find the dmg build files but it seems like the folder has been removed from the files section? Duncan can you please reupload it? Best Regards Miguel

Hi all, I'm still working on PSUD3 but thought I would pass it out in Beta form for comment to a small number of participants to get feedback on any potential major flaws. I'd like to keep the initial batch small as there will likely be numerous comments; many comments times many people will turn it into a circus, so I'd say about 10 people would be a good number to feed back initially on the very raw version. If the wheels don't fall off in grand style, this number could be increased after a couple of weeks. So... the next 10 people to reply to this message saying they want to be involved will receive a Beta copy of the software with a 30 day lifespan for them to have a look at and feed back via a private email list. It will just be Windows to start with; it makes sense to avoid fighting fires on multiple fronts until the basic structure is in place and correct. What I'm looking for is people who will run a bunch of different power supplies through, check accuracy / differences against PSUD2, and above all feed back the comments. Please avoid taking up a slot on the initial program if you've no in interest in doing that or just want to see what PSUD3 looks like out of curiosity. Some features, such as chart printing, are incomplete and the help file is probably more comedy than help right now, so please bear this in mind :) If you need a refresher on what PSUD3 is meant to look like, there's a video here -> https://www.youtube.com/watch?v=NfawEfqjcWY Regards, Duncan

Can PSUD2 model the "dual voltage" circuit? This is where the topology looks like a bridge circuit with four diodes, but you also tap the circuit to get a second output as a full-wave voltage. Typically the bridge voltage is about 2x the bridge voltage. Thanks. 73 de Martin, G3EDM

I have not touched a Mac in a decade. But a geek site reports that Mac is going to be less friendly toward un-signed apps: "... The right-click/control-click option for easily opening unsigned apps is no longer available. Users who want to open unsigned software will now need to go the long way around to do it: first, ... ... ..." https://arstechnica.com/gadgets/2024/08/macos-15-sequoia-makes-you-jump-through-more-hoops-to-disable-gatekeeper-app-checks/ The essay also says why this matters less for BIG developers, and is critical for "hobby" software like PSUD.