The V3 hardware contains a small MCU which acts as a power controller, with these tasks:
- soft-start: ensure that the current on the USB bus stays below 100mA until after higher current has been granted; avoid any peaks above 100mA
- power supply sequencing
- level 1: only power controller, GPIO are powered on
- level 2: soft start, prepare dc/dc converters
- level 3: USB controller is powered (core voltage, i/o voltage)
- level 4: FPGA is powered (core voltage, i/o voltage); the FPGA is responsible for controlling the image sensor power sequence (up, down)
- level 5: power for external GPS antenna is provided
- sleep modes
- power monitoring
- spi flash access control
- i2c slave for the usb controller
- switch from level 3 to 4 or 5
- switch down to lower levels
- report power state
- report sens_id1
- provide a small amount of persistent storage to the usb controller
- allow switching the fpga into slave-serial and master-spi modes
- reset for the usb controller
- control sys_led1
- monitor sens_id1
- provide a serial debug interface
?
Table of Contents
- Project Overview, Timeline and News
- Prototyp Version 2
- V2A Boards (updated: 22 Jun 2019)
- V3 power controller design
- Build Prototype Camera Overview
- Camera Control Interface
- Binary Overlay Format Specification
- Computer Specific Issues
- 8 Bit vs. 12 Bit Recording
- FITS header
- Camera Extension Unit Definition
- Packaging
- Konformität
- Image Sensors
- Software Downloads
Inhalt (Seiten in Deutsch)