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Refreshing XSIG's when one processor reboots or goes offline.
yellowfin684
I have two processors where I am using the XSIG symbols to communicate between the two. The problem of course with the older XSIG symbol is that they don't force the signals to stay in sync if one processor reboots or drops off line. From reading the help doc on the XSIG symbol, it looks like you can update or clear the values of the XSIG using \xFD or \xFC respectively. I have been tinker with updating the signals, but with no luck.
Would anyone have an example program on how to do this properly and efficiently? Also, I understand I could issue the update command on system start of either of the processors, but what about if one of the processors simply goes off line. Is there a socket signal I can monitor to track the online status of a processor? I've looked but I must be looking in the wrong place. Lastly, is there any reason to use the clear command to clear all the signals when trying to keep these in sync? Wouldn't I just want to issue update commands. Thanks a bunch |
I did that - I sent the signal to the opposite processor, jammed with
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the Xsig_tx$. I used an SIO on startup. You could implement some sort of heartbeat. OSC tied to an RING tied to an INIT, sent over the XSIG. On the opposite side, run it through a Analog One Shot and a Retriggerable One Shot. If the RTOS ever goes low, the other processor has stopped responding. Chris On 2/21/2011 1:34 PM, yellowfin684 wrote:
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Steve Kaudle
You mention the possibility of a processor going 'offline'. Should I take
that to mean the actual connection between the two is via IP? _____ From: Crestron@... [mailto:Crestron@...] On Behalf Of yellowfin684 Sent: Monday, February 21, 2011 2:35 PM To: Crestron@... Subject: [Crestron] Refreshing XSIG's when one processor reboots or goes offline. I have two processors where I am using the XSIG symbols to communicate between the two. The problem of course with the older XSIG symbol is that they don't force the signals to stay in sync if one processor reboots or drops off line. From reading the help doc on the XSIG symbol, it looks like you can update or clear the values of the XSIG using \xFD or \xFC respectively. I have been tinker with updating the signals, but with no luck. Would anyone have an example program on how to do this properly and efficiently? Also, I understand I could issue the update command on system start of either of the processors, but what about if one of the processors simply goes off line. Is there a socket signal I can monitor to track the online status of a processor? I've looked but I must be looking in the wrong place. Lastly, is there any reason to use the clear command to clear all the signals when trying to keep these in sync? Wouldn't I just want to issue update commands. Thanks a bunch |
yellowfin684
yeah, processor number 2 is remotely located and on its own switch. so if that switch ever goes down temporarily, the XSIGS would look to resync each other.
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--- In Crestron@..., "Steve Kaudle" <steve@...> wrote:
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yellowfin684
Chris, thanks a bunch. In your implementation, did you account for the processors going off line, or id your only update the XSIGs on boot. Just wondering...cause maybe in reality that will cover me for 99% of the situations where the the XSIGS could ever get out of sync.
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Great idea though on building my own heartbeat. I'll have to give it a shot. J --- In Crestron@..., Chris Niles <chris.niles.crestron@...> wrote:
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Steve Kaudle
Why not monitor the status of the IP connection (offline manager, output of
a TCP Client, etc. . .) and (re)send the update command on the appropriate edge of the status digital? _____ From: Crestron@... [mailto:Crestron@...] On Behalf Of yellowfin684 Sent: Monday, February 21, 2011 3:22 PM To: Crestron@... Subject: [Crestron] Re: Refreshing XSIG's when one processor reboots or goes offline. yeah, processor number 2 is remotely located and on its own switch. so if that switch ever goes down temporarily, the XSIGS would look to resync each other. --- In Crestron@... <mailto:Crestron%40yahoogroups.com> , "Steve Kaudle" <steve@...> wrote: [mailto:Crestron@... <mailto:Crestron%40yahoogroups.com> ] On Behalf Of yellowfin684like you can update or clear the values of the XSIG using \xFD or \xFCplace.
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enco.josh
I just finished a project where I had an AV2 communicating with two prodigy systems over UDP. I played around with a lot of complicated logic solutions to keep the two in sync, but I eventually found a simple solution that was very stable. I used the Activity Detection Device Extender from the UDP connection and a heartbeat on each side.
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The activity signal drives an SIO of \xFC to the RX$ of the XSIG, and a NOT of the activity signal also drives an SIO of \xFC to the RX$ of the XSIG. Also, an oscillator (1t hi_time, 5s, lo_time) drives the first digital input on the XSIG. I set the activity detection period to 11s to allow the systems to miss one heartbeat signal with out doing a resync, but that tolerance is up to you. If you put this logic on both processors, it will make sure both sides are always in sync. I can post an example program, but I think this is easy enough to understand. All you need is an XSIG, UDP/IP Connection with Activity Detection Device Extender, 2 SIOs, OSC, and a NOT. --- In Crestron@..., "yellowfin684" <jaredhaleck@...> wrote:
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