I looked at this issue some time back. As far as I can tell CPU (6802) can't do two data reads without CS toggling because it needs to fetch an instruction in between.
FM28V020 seems to be a 3.6V part, CPU board is a 5V design. It won't be happy seeing 5V long term.
Alternative suggested is FM18W08, which is a 5V part. However, it still has a potential issue. Dallas chip includes a low voltage lock out but FM18W08 doesn't have such protection and needs user to keep CE and WE in defined states all the time. Following text is from FM18W08 datasheet "It is the user’s responsibility to ensure that chip enable is HIGH to prevent accesses below VDD min. (2.7 V)." Unfortunately, supervisor chip (TL7705) output is undefined until 3.6V, there is no deliberate mechanism to protect the memory.
Although it works for many, it is not robust by design. FYI, I also installed an FM18W08 to try it out and it didn't lose its data yet. Most likely I will add a lower minimum supply voltage supervisor chip to eliminate this risk.
There is also a logic level incompatibility, FM18W08 guaranteed Vih is 0.7*vdd=3.5V but CE comes from a PAL chip at TTL levels (Voh can be lower than 3.5V). A pull up may fix it but at guaranteed specs logic levels are not compatible.
Ozan
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On Sun, Feb 4, 2024 at 10:14 PM, Ram wrote:
As observed, FRAMs may work but when they don't, the reason is usually
attributed to the fact that the CE pin needs to be toggled for each write in
many popular FRAMs whereas in the Tek scope it is held steady. However there
IS at least one FRAM which does not need CE to be toggled and that is
PM28V020. From the datasheet:
"The FM28V020 is designed to be a drop-in replacement for standard
asynchronous SRAMs. The device does not require CE to toggle for each new
address. CE may remain LOW indefinitely while VDD is applied."
Not sure if it is the only potential issue. FWIW I tried it in my 2465A and it
works.
Best - Ram
