Keyboard Shortcuts
ctrl + shift + ? :
Show all keyboard shortcuts
ctrl + g :
Navigate to a group
ctrl + shift + f :
Find
ctrl + / :
Quick actions
esc to dismiss
Likes
Search
CLK0,/CLK1 - VFO/BFO
|
HI All,
I've been working on putting together another BITX40. I didn't leave myself enough room in the old lashup for mods and additions. This time I decided to use SMA connectors for all the RF, VFO/BFO/RFOUT. Nice to have real fittings instead of clips. Anyway, as I route the new wiring it would be more convenient to switch the BFO to CLK0 and the BFO to CLK1. Then I could avoid having the coax cross as it goes to the board. I seem to remember that there is some reason that the VFO was on CLK1, board cross talk maybe or something. Anyone know why that is? Thanks! Jonathan - KK6RPX |
|
Vince Vielhaber
Actually the VFO uses CLK2. I'm also building up a second one for mods
toggle quoted message
Show quoted text
and the first mod is my own VFO which utilizes both CLK2 for the VFO and CLK0 for the BFO. Odd thing tho, I couldn't get 12MHZ out of CLK0 with the si5351 library that the Raduino uses. Switching to Pavel's library solved that problem tho. My guess is because the other library uses PLL-A for CLK0-2 and PLL-B for CLK3-7. The problem is the si5351A only has CLK0-2 so that library sticks us with only PLL-A. Pavel's doesn't do that - hence his 2 of 3 rule. Vince. HI All, --
Michigan VHF Corp. |
|
I'll have to look and see which Si5351 lib I'm using but I get the 12MHz out. However, do you know of any reason not to switch CLK2 for CLK1?
toggle quoted message
Show quoted text
Thanks! On 6/26/2017 9:29 AM, Vince Vielhaber wrote:
Actually the VFO uses CLK2. I'm also building up a second one for mods |
|
Best to use the two CLK pins physically far apart first, CLK1 when turned on can have crosstalk with CLK0 and CLK2.
toggle quoted message
Show quoted text
On Mon, Jun 26, 2017 at 09:51 am, Jonathan Peakall wrote: However, do you know of any reason not to switch CLK2 for CLK1?? |
|
Vince Vielhaber
Off hand, no. But the uBitX uses all three. CLK2 for the first
toggle quoted message
Show quoted text
conversion, CLK1 for the second and CLK0 for the BFO. As to the 12MHz, maybe it was just the VFO freq that I had tuned. Don't know, but it worked fine under 10MHz, didn't try between 10 and 12 to see where it cut out. Vince. I'll have to look and see which Si5351 lib I'm using but I get the 12MHz --
Michigan VHF Corp. |
开云体育Dang. I cant seem to use the correct output number when I am writing! Argh.So, it seems that swapping the two should be ok. Meaning (may I please get this right!) use CLK0 for VFO and CLK2 for BFO. For some reason I seemed to remember reading that CLK2 was used for the VFO for some reason. Anybody remember anything along those lines? Thanks! On 6/26/2017 10:35 AM, Jerry Gaffke via
Groups.Io wrote:
Best to use the two CLK pins physically far apart first, CLK1 when turned on can have crosstalk with CLK0 and CLK2. |
|
Haven't tried it, but Etherkit library should be able to get most any arbitrary freq
toggle quoted message
Show quoted text
out of CLK0 while CLK2 is independently generating the VFO. Etherkit library freezes VCOA at 800mhz, then uses the output multisynth fractional dividers to create arbitrary clocks from that 800mhz. ? Since VCOA is never changed after initialization (unless you exceed 100mhz fout) there is never any need to reset it and create a tuning glitch. Pavel seems to be getting by with moving the VCO's around a limited amount without a reset. He keeps it as close to 900mhz as possible while using an even integer output divider. Each of his two possible output clocks (not 3) gets its own VCO A much different scheme. ?Will be interesting to compare the two. I'm looking at what it would take to run the Si5351 from a minimum of flash/RAM, significantly smaller than Pavels.? Are you sure you are getting two simultaneous outputs using Pavel's code? I though I might have seen a bug in how VCOB got loaded, though could be a documentation error. Jerry, KE7ER . On Mon, Jun 26, 2017 at 09:33 am, Vince Vielhaber wrote:
Odd thing tho, I couldn't get 12MHZ out of CLK0 with the si5351 library that the Raduino uses. |
|
Vince Vielhaber
Definitely getting two different freqs. I had to use the example code and
toggle quoted message
Show quoted text
the docs to do it tho. The first attempt produced a very unstable CLK0, but after doing the extra steps it was rock solid. Vince. Haven't tried it, but Etherkit library should be able to get most any --
Michigan VHF Corp. |
|
Pavel Milanes Costa
Hi Jerry,
I'm in CARNIVAL season here in my town, so family fun is first, I have played with your code about a+b/c but not enough yet. El 26/06/17 a las 13:49, Jerry Gaffke via Groups.Io escribió: Are you sure you are getting two simultaneous outputs using Pavel's code?I'm interested in the bug you mention... 73 de Pavel CO7WT. |
|
The possible bug is here, it would affect the frequency from PLLB:
toggle quoted message
Show quoted text
// this registers are not 8 bytes apart
if (clk == 0) {
i2cWrite(27, MSNx_P3 & 255);
i2cWrite(28, (MSNx_P1 & 196608) >> 16);
} else {
i2cWrite(35, MSNx_P1 & 255);
i2cWrite(36, (MSNx_P2 & 0x00030000) >> 10);
}
Register 36 in the summary on page 11 of AN619 does not agree with the complete description of register 36 on page 31, I think the summary is wrong. ?So register 36 should get MSNB_P1[1-16] in the two LSB's. Also, register 35 gets MSNB_P3[7-0], not MSNB_P1[7-0] ?? I think all registers for PLLB are an offset of 8 from PLLA registers, no need for the special case of "if (clk==0) {"? No worries about my shift scheme on computing b and c. I am looking at a total rewrite of the entire library. Have fun at carnival! Are any of your family members in a band? Jerry On Mon, Jun 26, 2017 at 11:02 am, Pavel Milanes Costa wrote:
I'm in CARNIVAL season here in my town, so family fun is first, I have played with your code about a+b/c but not enough yet. |
|
CLK0 and CLK1 are grouped together. ?CLK2 is isolated off by itself.
toggle quoted message
Show quoted text
So likely best to use CLK2 for the most critical signal source, whatever that is. Ideally CLK0 and CLK1 would be locked together to reduce birdies. ?Perhaps CLK1 is a 12mhz BFO and CLK0 is set to 5*12=60mhz for the first mixer of a double conversion rig. ? Better yet, blow an extra $1USD for a second Si5351, and shield them from each other. ?But then you need some way of talking to them both via I2C, and they likely have the same address of 0x60. ? ?Perhaps use an analog switch or logic gates to turn on the I2C clock into one Si5351 at a time. Jerry, KE7ER On Mon, Jun 26, 2017 at 10:47 am, Jonathan Peakall wrote: So, it seems that swapping the two should be ok. Meaning (may I please get this right!) use CLK0 for VFO and CLK2 for BFO. |
|
Pavel Milanes Costa
开云体育Hi Jerry et all. Sometimes one gets stuck in language tricks and different
cultures, it is possible that what we call here "Carnaval" and
which I translated as "carnival" is not strictly the right
word. As you my guess, since Saturday I'm
getting out of the house at nightfall to enjoy music, dance,
beer, plays, etc; with kids and family. So no much free time for
Arduinos here...? ;-) In Spanish, use google translate to get it in your language: Pictures thanks to Google Images ------ About the "BUG" I have to watch it closely, but the AN as the Datasheet are not quite well documented, there are some errors and omissions... I don't remember exactly why I coded it that way... I have to check it out.... after carnival... 73 de CO7WT. El 26/06/17 a las 14:26, Jerry Gaffke
via Groups.Io escribió:
The possible bug is here, it would affect the frequency from PLLB: |
|
Pavel Milanes Costa
El 26/06/17 a las 15:29, Jerry Gaffke via Groups.Io escribió:
Better yet, blow an extra $1USD for a second Si5351, and shield them from each other. But then you need some way of talking to them both via I2C, and they likely have the same address of 0x60. Perhaps use an analog switch or logic gates to turn on the I2C clock into one Si5351 at a time.A 74hc4066 switch is a great tool here... I played with a config like this before and worked like a charm: 2 x Si5351, just one I2C bus addressed to a different Si chip every time via an arduino extra pin to make the switch. But beware, I have to put a 10k resistor on the I2C bus at the Arduino and at every I2C Si5351 I2C (six resistors, two at the arduino, two at one Si5351 and two at the other), as switching without it makes some times a pulses that keep the Si5351 in a non-normal state and unresponsive. 73 de CO7WT. |
|
Vince Vielhaber
On 06/26/2017 03:39 PM, Pavel Milanes Costa wrote:
No need for an extra chip or fancy chip selections. Tie A0 on the si5351 LOW for 0x60 or tie it HIGH for 0x61. Problem solved. Vince. -- Michigan VHF Corp. |
|
Unfortunately, no A0 pin on my cheap MSOP10 part.
toggle quoted message
Show quoted text
An Si5351 with the A0 pin costs 10x the price. Though you can get the MSOP10 part custom programmed at the factory for?different I2C addresses, and/or programmed to power up spitting out the required frequencies. Jerry? On Mon, Jun 26, 2017 at 01:17 pm, Vince Vielhaber wrote: No need for an extra chip or fancy chip selections. Tie A0 on the si5351 LOW for 0x60 or tie it HIGH for 0x61. Problem solved. |
|
That sounds like Carnival. ?
toggle quoted message
Show quoted text
Even if it doesn't quite line up with Lent. And sounds like a great way to celebrate community. Jerry On Mon, Jun 26, 2017 at 12:43 pm, Pavel Milanes Costa wrote: Sometimes one gets stuck in language tricks and different cultures, it is possible that what we call here "Carnaval" and which I translated as "carnival" is not strictly the right word. |
|
Vince Vielhaber
Well you're just bursting with good news, aren't ya?
toggle quoted message
Show quoted text
Vince. On 06/26/2017 05:26 PM, Jerry Gaffke via Groups.Io wrote:
Unfortunately, no A0 pin on my cheap MSOP10 part. --
Michigan VHF Corp. |
开云体育Page 16 of the Si5351 shows how you can connect two Si5351s to the same I2C bus. Mike K5ESS ? From: [email protected] [mailto:[email protected]] On Behalf Of Jerry Gaffke via Groups.Io ? CLK0 and CLK1 are grouped together. ?CLK2 is isolated off by itself. So, it seems that swapping the two should be ok. Meaning (may I please get this right!) use CLK0 for VFO and CLK2 for BFO. |
开云体育Should have read ALL the postings before mine. Mike K5ESS ? From: [email protected] [mailto:[email protected]] On Behalf Of Jerry Gaffke via Groups.Io ? Unfortunately, no A0 pin on my cheap MSOP10 part. No need for an extra chip or fancy chip selections. Tie A0 on the si5351 LOW for 0x60 or tie it HIGH for 0x61. Problem solved. |
|
I'd like to create as smoothly tuning VFO.
toggle quoted message
Show quoted text
This might mean updates to the Si5351 every millisecond, with just a few hz difference between updates. Here's a few things to consider for those of you curious about Si5351 innards. Using either the etherkit library or Pavel's code, it takes 8 register writes to change the Si5351 frequency. This can be sped up by using I2c facility for writing to consecutive registers, but assuming a 100khz (max) I2c clock, that's still nearly a millisecond where the output clock is not either the old value or the new value, just some random value as all those registers get changed. Unfortunately, the Si5351 does not buffer the contents of those 8 registers, no way around those partial results. So my smoothly tuning VFO might spend most of its time off at other frequencies. In Pavels code, the registers control the PLL, perhaps the PLL has a low enough bandwidth loop filter that it doesn't wander far during the transition. ?I doubt it.? In the etherkit code, each of the 8 register writes to the output msynth have an immediate effect. The CLK1 output pin can select either output msynth1 or output msynth0 as a source, so could pingpong between the two sources, using the stable one as we update the other. We still have a momentary glitch as the clocks switch, but now we're mostly on frequency. And we still have msynth2 and the CLK2 pin available as a second output. This might be a case where we want to use CLK1 and CLK2, but not CLK0. The CLK0 output cannot select any output msynth other than msynth0, CLK2 can only select msynth0 or msynth2, so we'd still be stuck with not using CLK0. Alternately, we could have msynth0 always driving CLK0, but pingpong between PLLA and PLLB as the source to msynth0. ?In this case with both VCO's changing, it would be difficult to create a second output clock that's stable. A good DDS chip might be a better solution than the Si5351 if we really wanted smooth transitions. But we could get close, and the price is right. Jerry On Mon, Jun 26, 2017 at 10:35 am, Jerry Gaffke wrote:
|
to navigate to use esc to dismiss