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SI5351 simultaneous clock changes
#ubitx-help
John
Taking a short-cut from reading the SI5351 datasheet and after going through Jerry's code in the ubitx_si5351 source, I believe that two clocks can be changed simultaneously.
The purpose of this is for using the 1st IF shift to produce a TX gain control. I would like to avoid shifting the transmit frequency even for a few micro seconds if I use two successive? calls to the?si5351bx_setfreq() method.? My understanding is that I can write the data to the two series of (8 + 1) registers, then do a clock enable for all the enabled clocks with? i2cWrite(3, si5351bx_clken) to affect the changes in two clocks at the same time. Since I would shift both by the same value, I would expect the result to be virtually simultaneous. Am I correct or is there a better method? Thanks and 73, John (VK2ETA) |
When I wrote that code, I assumed the output clock would be jumping around like crazy as the registers got loaded.
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This chip is primarily out there to replace a bunch of the older fixed 4 pin crystal oscillators after all. But amazingly enough, I found I could update the clock in 1hz increments and it swept cleanly in frequency just like an analog vfo. Not so much as a runt clock pulse, no suggestion of any disruption when the frequency changed. The only hint of this in the datasheet or AN619 is the statement in the upper right of the si5351 datasheet stating "Glitchless Frequency Changes". Nothing in the register descriptions says exactly when or how the clock frequency changes at the output pin. My best guess is that the switch will occur when the 8'th register of that burst write occurs. I don't really know. You could do a Serial.write() plus a 5 second delay after each register write, see when the frequency does change. Could probably load up all the registers for both clocks up to that final register,? then quickly write both final registers.?? Since the two final registers are not consecutive, you can't do a burst write. Single register writes involve sending out the i2c address, register address, and data, about 30 i2c clocks. Max i2c clock rate is 400khz (I think the Nano defaults to 100khz), so 30/400khz = 75us between the two clock updates. Let us know what you find out. Not obvious to me why you need to change the gain while transmitting. Just shut down the transmitter for a few milliseconds when transitioning the power level. Jerry, KE7ER On Sun, Apr 1, 2018 at 10:56 pm, John wrote: Taking a short-cut from reading the SI5351 datasheet and after going through Jerry's code in the ubitx_si5351 source, I believe that two clocks can be changed simultaneously. |
John
Thanks Jerry, great ideas.?
I will try the delayed single write and report what happens. My objective is to have a software ALC or power limiter for SSB (and mainly for digital modes) where I can control the output power. Since I measure the forward power continuously my thinking is to use the slope of the first IF filter like I do with the software AGC. In Rx there is a very slight "pop" when the increase of both clock 1 and 2 occurs (see Ian's Youtube video) and I suspect this is related to the time difference between the changes. The effect is barely noticeable, but in TX I may for a millisecond or so transmit on a frequency 4 or 6 khz away from the current one. Since I don't think that is good practice I am researching how to avoid it. Worse case scenario I will disable the clocks, change frequency then re-enable them as you mentioned. Hope that makes sense. Thanks and 73, John (VK2ETA) |
I'm not convinced there's a need for continuous ALC during transmit
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But would be very cool to set the appropriate power out level when tuning up on a new band. Or better yet, tune up on each band into a dummy load during calibration, and store appropriate 45mhz IF shifts into a lookup table. Jerry On Mon, Apr 2, 2018 at 03:19 am, John wrote: Worse case scenario I will disable the clocks, change frequency then re-enable them as you mentioned. |
John
Hello Jerry,
Tried both methods and came back to your idea..hihi The lookup table (four frequency points, plus interpolation) does the job better. For info about the si5351 clock updates, the chip waits for the 8th register to be written to effect the frequency change. I wrote a method to do as you said changing both clocks first 7 registers then quickly writing the 8th ones. It reduces the clicks but not 100%. Plus the FWD power reading gets messed up when the ATU tunes. So now I have low, medium and high power dialled up in the menu. Neat. Thanks for your help. 73, John (VK2ETA) |
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