?

OK, the names DO matter.? I was confused by the caching performed by the webFPGA IDE.? Honestly, there's a bit more "magic" happening in there than I'm comfortable with.
The canonical names of the pins are hidden.? Somewhere, there must be a config file, but it's not presented to me the user.? I tried an experiment.? I cruised the list of sample programs and pulled out all the names of inputs & outputs that they were using.? I then modified the "blink LED" program - first, to blink really fast - about 5 kHz.? Then had it toggle
ALL the named pins.? Went up and down the sides of the unit with my scope, and found 5kHz on 8 pins.? Modified the program to send the waveform for just one pin, and scoped
around for it... That way, I found names or labels that work for 8 pins.?

?? What now?? I guess I'm going to try reinventing some simple wheels.?? Maybe a barrel shifter.? A BDC to seven segment decoder.? A divide by 10.? The object is just to gain
some familiarity with the language & tools.

???????????????????? - Jerry, KF6VB





??

?

All very true but do keep in mind that open source logic IP blocks can vary greatly in quality just like open source software. I'm reminded of an evaluation at work years ago of various HW implementations of AES (the crypto algorithm). The conclusion was that producing a technically correct AES IP block wasn't hard. There were lots around. Producing an efficient/fast block was another thing. That took time and effort. (And at the time a good one cost money.)?

And like open source SW using them may require digging into the block to understand how it works and what its interfaces look like. I expect that the nice GUI provided by e.g. the Quartus tool from Intel relies on the blocks you drop into place to comply with some carefully defined interface standards such as the using the Altera defined bus(es) to transfer data. Random IP from the internet probably won't do that and you'll need to stitch it into place.

I'm not trying to discourage anyone here. This is doable and definitely a learning experience.

One final warning I'd make for anyone going the route of getting student access. I completely agree that anyone can be a student. But be careful if the project relying on that fpga becomes a product. You may find you've violated your student license. I'm not a lawyer and I'm not making any threats here, just warning people to watch their own personal liability.

On Sat, Sep 9, 2023 at 09:02 AM, K9HZ wrote:

Yeah I did see that about the IP blocks…. But a lot of people have published them now and there are lots of GITHUB clearing house projects that have them for free.? Also, like I said… for educators and students there is little or no cost.? Everyone could be a student?

?

It tried Quartis last night and it seems pretty straight forward (for a hardware designer).? Seems like business as usual, building everything out of basic blocks like we did in the late 70’s and early 80’s.

?

?

Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ

?

Owner - Operator

Big Signal Ranch – K9ZC

Staunton, Illinois

?

Owner – Operator

Villa Grand Piton – J68HZ

Soufriere, St. Lucia W.I.

Rent it:

?

Moderator: North American QRO Group at Groups.IO.

Moderator: Amateur Radio Builders Group at Groups.IO.

?

email:? bill@...

?

?

From: [email protected] <[email protected]> On Behalf Of Greg KF5N
Sent: Saturday, September 9, 2023 6:26 AM
To: [email protected]
Subject: Re: [AmateurRadioBuilders] FPGA programming IDC

?

You will find that the FPGA domain is more proprietary.? "IP" is the key term.? IP blocks take a lot of debugging to make them robust.? Timing constraints need to be applied.? I bought a book which is only discussion of timing constraints.
For smaller hobby circuits, the timing constraints won't matter.

Quartus is the design and verification tool that I used for my little FPGA projects.? It's a big tool.
I used SystemVerilog, which has more features than its predecessor Verilog.? What is supported depends on the FPGA.? VHDL is another popular language, but don't forget, it's not programming, it is hardware abstraction.
Intel bought Altera, and I think they were the original developers of the Quartus tool suite.

73 Greg KF5N

?

Yeah I did see that about the IP blocks…. But a lot of people have published them now and there are lots of GITHUB clearing house projects that have them for free.? Also, like I said… for educators and students there is little or no cost.? Everyone could be a student?

?

It tried Quartis last night and it seems pretty straight forward (for a hardware designer).? Seems like business as usual, building everything out of basic blocks like we did in the late 70’s and early 80’s.

?

?

Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ

?

Owner - Operator

Big Signal Ranch – K9ZC

Staunton, Illinois

?

Owner – Operator

Villa Grand Piton – J68HZ

Soufriere, St. Lucia W.I.

Rent it:

?

Moderator: North American QRO Group at Groups.IO.

Moderator: Amateur Radio Builders Group at Groups.IO.

?

email:? bill@...

?

?

From: [email protected] <[email protected]> On Behalf Of Greg KF5N
Sent: Saturday, September 9, 2023 6:26 AM
To: [email protected]
Subject: Re: [AmateurRadioBuilders] FPGA programming IDC

?

You will find that the FPGA domain is more proprietary.? "IP" is the key term.? IP blocks take a lot of debugging to make them robust.? Timing constraints need to be applied.? I bought a book which is only discussion of timing constraints.
For smaller hobby circuits, the timing constraints won't matter.

Quartus is the design and verification tool that I used for my little FPGA projects.? It's a big tool.
I used SystemVerilog, which has more features than its predecessor Verilog.? What is supported depends on the FPGA.? VHDL is another popular language, but don't forget, it's not programming, it is hardware abstraction.
Intel bought Altera, and I think they were the original developers of the Quartus tool suite.

73 Greg KF5N

?

?

Since I have the card, I'm working through the tutorial on webfpga.com
( book.webfpga.io ).

Starting with the simplest example - turn on the LED when you push the
button- I'm
playing with it. Sticking in syntax errors to see what happens. Here's
something interesting:
they declare the LED as "WF_LED", and the button as "WF_BUTTON". What
happens if I change the names? Say "BOBBY" instead of "WF_LED"...? It
works the same! The name doesn't matter!
I can only guess that it assigns the first signal to pin 1, the second
to pin 2 etc.

...or something like that.

It doesn't care about extra semicolons. Stick in 1, stick in 5, no
difference. But if I
stick in semicolons before "module" it fails.

ETC.

The card uses a Lattice FPGA, and it's compatible with their tools,
and also the open-source
"IceStorm" project.

- Jerry, KF6VB




On 2023-09-09 06:05, K9HZ wrote:

Very nice John…. Thanks. This is a great place to start from in my
learning process… dissect it and see how it works…

DR. WILLIAM J. SCHMIDT - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ
PJ2/K9HZ VP2EHZ

Owner - Operator

Big Signal Ranch – K9ZC

Staunton, Illinois

Owner – Operator

Villa Grand Piton – J68HZ

Soufriere, St. Lucia W.I.

Rent it: [1]

Moderator: North American QRO Group at Groups.IO.

Moderator: Amateur Radio Builders Group at Groups.IO.

email: bill@...

FROM: [email protected] <[email protected]>
ON BEHALF OF John Melton via groups.io
SENT: Saturday, September 9, 2023 6:36 AM
TO: [email protected]
SUBJECT: Re: [AmateurRadioBuilders] FPGA programming IDC

All the FPGA code for the HPSDR and Apache Labs radios are in
along with the protocol
documentation.

Each radios source code is in the .qar files which is an archive saved
from the Quartus IDE.

There is also a good paper there on timing closure by Joe Martin, K5SO



-- John G0ORX

On Sat, 9 Sept 2023, 12:26 Greg KF5N, <greg.electricity@...>
wrote:

You will find that the FPGA domain is more proprietary. "IP" is the
key term. IP blocks take a lot of debugging to make them robust.
Timing constraints need to be applied. I bought a book which is
only discussion of timing constraints.
For smaller hobby circuits, the timing constraints won't matter.

Quartus is the design and verification tool that I used for my
little FPGA projects. It's a big tool.
I used SystemVerilog, which has more features than its predecessor
Verilog. What is supported depends on the FPGA. VHDL is another
popular language, but don't forget, it's not programming, it is
hardware abstraction.
Intel bought Altera, and I think they were the original developers
of the Quartus tool suite.

73 Greg KF5N

Links:
------
[1]
[2] /g/AmateurRadioBuilders/message/2491
[3] /mt/101248628/243852
[4] /g/AmateurRadioBuilders/post
[5] /g/AmateurRadioBuilders/editsub/243852
[6]
/g/AmateurRadioBuilders/leave/11522011/243852/920863695/xyzzy

?

Yes as I remember there was not a lot of open source or free tools IDEs etc. And no one posted any kind of source code except rudimentary examples when I was working with FGPAs in college. ?I think the chip I was working with was a Xilinx spartan 3 and the dev board and VHDL/Verilog IDE license where quite pricy, I got a student discount and the kit still cost several hundred as I recall, shot my pizza budget for a good few months. ?I think I may still have that dev board, might be fun to do something with it.

Very nice John…. Thanks. This is a great place to start from in my
learning process… dissect it and see how it works…

DR. WILLIAM J. SCHMIDT - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ
PJ2/K9HZ VP2EHZ

Owner - Operator

Big Signal Ranch – K9ZC

Staunton, Illinois

Owner – Operator

Villa Grand Piton – J68HZ

Soufriere, St. Lucia W.I.

Rent it: www.VillaGrandPiton.com [1]

Moderator: North American QRO Group at Groups.IO.

Moderator: Amateur Radio Builders Group at Groups.IO.

email: bill@...

FROM: [email protected] <[email protected]>
ON BEHALF OF John Melton via groups.io
SENT: Saturday, September 9, 2023 6:36 AM
TO: [email protected]
SUBJECT: Re: [AmateurRadioBuilders] FPGA programming IDC

All the FPGA code for the HPSDR and Apache Labs radios are in
along with the protocol
documentation.

Each radios source code is in the .qar files which is an archive saved
from the Quartus IDE.

There is also a good paper there on timing closure by Joe Martin, K5SO



-- John G0ORX

On Sat, 9 Sept 2023, 12:26 Greg KF5N, <greg.electricity@...>
wrote:

You will find that the FPGA domain is more proprietary. "IP" is the
key term. IP blocks take a lot of debugging to make them robust.
Timing constraints need to be applied. I bought a book which is
only discussion of timing constraints.
For smaller hobby circuits, the timing constraints won't matter.

Quartus is the design and verification tool that I used for my
little FPGA projects. It's a big tool.
I used SystemVerilog, which has more features than its predecessor
Verilog. What is supported depends on the FPGA. VHDL is another
popular language, but don't forget, it's not programming, it is
hardware abstraction.
Intel bought Altera, and I think they were the original developers
of the Quartus tool suite.

73 Greg KF5N

Links:
------
[1]
[2] /g/AmateurRadioBuilders/message/2491
[3] /mt/101248628/243852
[4] /g/AmateurRadioBuilders/post
[5] /g/AmateurRadioBuilders/editsub/243852
[6]
/g/AmateurRadioBuilders/leave/11522011/243852/920863695/xyzzy

?

?

?

You will find that the FPGA domain is more proprietary.? "IP" is the key term.? IP blocks take a lot of debugging to make them robust.? Timing constraints need to be applied.? I bought a book which is only discussion of timing constraints.
For smaller hobby circuits, the timing constraints won't matter.

Quartus is the design and verification tool that I used for my little FPGA projects.? It's a big tool.
I used SystemVerilog, which has more features than its predecessor Verilog.? What is supported depends on the FPGA.? VHDL is another popular language, but don't forget, it's not programming, it is hardware abstraction.
Intel bought Altera, and I think they were the original developers of the Quartus tool suite.

73 Greg KF5N

?

Yes they do… BUT there is a little it of a catch.? YOU can build functions from things like gates (PLL for example), OR you can buy a license for a pre-canned PLL function (called Ips) from them or someone who makes those blocks.? If you get an account and select “Student” or “Educator” most of it is free…

?

?

Dr. William J. Schmidt - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ PJ2/K9HZ VP2EHZ

?

Owner - Operator

Big Signal Ranch – K9ZC

Staunton, Illinois

?

Owner – Operator

Villa Grand Piton – J68HZ

Soufriere, St. Lucia W.I.

Rent it:

?

Moderator: North American QRO Group at Groups.IO.

Moderator: Amateur Radio Builders Group at Groups.IO.

?

email:? bill@...

?

?

?

Looks like that's Intel software. Do they give it away?

- Jerry, KF6VB

On 2023-09-08 16:39, K9HZ wrote:

This is the graphic builder I was told about. As much as I hate
software, looks like this might not be so bad…?

DR. WILLIAM J. SCHMIDT - K9HZ J68HZ 8P6HK ZF2HZ PJ4/K9HZ VP5/K9HZ
PJ2/K9HZ VP2EHZ

Owner - Operator

Big Signal Ranch - K9ZC

Staunton, Illinois

Owner - Operator

Villa Grand Piton - J68HZ

Soufriere, St. Lucia W.I.

Rent it: [1]

Moderator: North American QRO Group at Groups.IO.

Moderator: Amateur Radio Builders Group at Groups.IO.

email: bill@...



Links:
------
[1]
[2] /g/AmateurRadioBuilders/message/2482
[3] /mt/101248628/243852
[4] /g/AmateurRadioBuilders/post
[5] /g/AmateurRadioBuilders/editsub/243852
[6]
/g/AmateurRadioBuilders/leave/11522011/243852/920863695/xyzzy